Computer System Architecture

121. Which signal on the bus indicates that request from process arbitration is to be processed:

  1. BAL
  2. BREQ
  3. BM4
  4. DBA

Correct answer: (B)
BREQ

122. Which signal is exchange information by bus:

  1. BECH
  2. BM4
  3. BAL
  4. All of these

Correct answer: (A)
BECH

123. Which signal on bus applies +1 to the priority of resolution circuits of the arbitration designate a new arbitration:

  1. BM4
  2. BAL
  3. BNA
  4. DBA

Correct answer: (C)
BNA

124. Which signal create 3 lines of bus in which signals from the encoded number of processors:

  1. BM1 to BM3
  2. BAL
  3. Both
  4. None of these

Correct answer: (A)
BM1 to BM3

125. Which signal request the validation signal make active if its logic level is 0 and validate signals from BM1 to BM3:

  1. BAL
  2. BM4
  3. BNA
  4. All of these

Correct answer: (B)
BM4

126. Which signal represents synchronization signal decided by interprocess arbitration with a certain delay or signal DMA:

  1. BAL
  2. BNA
  3. Both
  4. None of these

Correct answer: (A)
BAL

127. In which condition only one process holds a resource at a given time:

  1. Mutual exclusion
  2. Hold and wait
  3. Both
  4. None of these

Correct answer: (A)
Mutual exclusion

128. In which condition one process holds the allocated resources and other waits for it:

  1. No preemption
  2. Hold and wait
  3. Mutual exclusion
  4. All of these

Correct answer: (B)
Hold and wait

129. In which condition resource is not removed from a process holding:

  1. Synchronization problem
  2. No preemption
  3. Hold and wait
  4. None of these

Correct answer: (B)
No preemption

130. In which condition busy waiting, programmer error, deadlock or circular wait occurs in interprocessing:

  1. Synchronization problem
  2. No preemption
  3. Hold and wait
  4. None of these

Correct answer: (A)
Synchronization problem

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