Computer System Architecture

91. ____________ method is used to establish priority by serially connecting all devices that request an interrupt:

1. Polling
2. Daisy chaining
3. Priority
4. None of these

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92. In daisy chaining device 0 will pass signal only if it has:

1. Interrupt request
2. No interrupt request
3. Both a & b
4. None of these

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93. VAD stands for:

1. Vector address
2. Symbol address
3. Link address
4. None of these

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94. ____________ interrupt method uses a register whose bits are set separately by interrupt signal for each device:

1. Parallel priority interrupt
2. Serial priority interrupt
3. Both a & b
4. None of these

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95. ____________ register is used whose purpose is to control status of each interrupt request in parallel priority interrupt:

1. Mass
2. Mark
3. Make
4. Mask

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96. The ANDed output of bits of interrupt register and mask register are set as input of:

1. Priority decoder
2. Priority encoder
3. Priority decoder
4. Multiplexer

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97. Which 2 output bits of priority encoder are the part of vector address for each interrupt source in parallel priority interrupt:

1. A0 and A1
2. A0 and A2
3. A0 and A3
4. A1 and A2

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98. of A0 and A1 output bits of priority encoder in parallel priority:

1. Tell data bus which device is to entertained and stored in VAD
2. Tell subroutine which device is to entertained and stored in VAD
3. Tell subroutine which device is to entertained and stored in SAD
4. Tell program which device is to entertained and stored in VAD

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99. When CPU invokes a subroutine it performs following functions:

1. Pushes updated PC content(return address) on stack
2. Loads PC with starting address of subroutine
3. Loads PC with starting address of ALU
4. Both a & b

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100. DMAC stands for:

1. Direct memory access controller
2. Direct memory accumulator controller
3. Direct memory access content
4. Direct main access controller

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